imple
b008b37d49
Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
50 lines
1.8 KiB
Markdown
50 lines
1.8 KiB
Markdown
# Phase 1 - ALU + M Unit
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## Context
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This phase builds the arithmetic core of the CPU. The ALU handles simple single-cycle
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operations; the M unit handles multiplication and division with an explicit handshake.
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## Goals
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- Build and verify a combinational RV32I ALU.
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- Build and verify a multi-cycle RV32M unit.
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- Learn simulation-first hardware development before system integration.
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## New Concepts
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- ALU: arithmetic logic unit; performs integer arithmetic, comparisons, shifts, and logic.
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- DSP slice: FPGA hard block optimized for multiplication and arithmetic.
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- Multi-cycle unit: block that takes several clocks to produce a result.
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- Handshake: protocol using signals such as start, busy, done, valid, or ready.
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## How To Think About It
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The ALU is pure combinational decision logic. The M unit is a small protocol machine. Do
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not force division into the ALU just because it is mathematically an arithmetic operation.
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## Learning Tasks
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- Understand signed versus unsigned interpretation of the same 32 bits.
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- Work through RISC-V division edge cases by hand.
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- Draw the M-unit state machine before writing RTL.
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## Pitfalls
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- Implementing a combinational divider and then fighting timing forever.
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- Treating signed comparisons as unsigned or vice versa.
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- Dropping `done` or accepting a new `start` at the wrong time.
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## Tooling And Testing
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- Start with small deterministic test vectors, then add randomized checks.
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- Use waveform inspection to confirm handshake timing, not only final results.
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- Synthesize early to see whether multiply infers DSP resources.
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## References
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- RISC-V unprivileged ISA, integer and M extension chapters: https://riscv.org/technical/specifications/
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- AMD/Xilinx DSP48 documentation: https://docs.xilinx.com/
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- Project F FPGA arithmetic articles: https://projectf.io/posts/
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