# Phase 1 - ALU + M Unit

## Context

This phase builds the arithmetic core of the CPU. The ALU handles simple single-cycle
operations; the M unit handles multiplication and division with an explicit handshake.

## Goals

- Build and verify a combinational RV32I ALU.
- Build and verify a multi-cycle RV32M unit.
- Learn simulation-first hardware development before system integration.

## New Concepts

- ALU: arithmetic logic unit; performs integer arithmetic, comparisons, shifts, and logic.
- DSP slice: FPGA hard block optimized for multiplication and arithmetic.
- Multi-cycle unit: block that takes several clocks to produce a result.
- Handshake: protocol using signals such as start, busy, done, valid, or ready.

## How To Think About It

The ALU is pure combinational decision logic. The M unit is a small protocol machine. Do
not force division into the ALU just because it is mathematically an arithmetic operation.

## Learning Tasks

- Understand signed versus unsigned interpretation of the same 32 bits.
- Work through RISC-V division edge cases by hand.
- Draw the M-unit state machine before writing RTL.

## Pitfalls

- Implementing a combinational divider and then fighting timing forever.
- Treating signed comparisons as unsigned or vice versa.
- Dropping `done` or accepting a new `start` at the wrong time.

## Tooling And Testing

- Start with small deterministic test vectors, then add randomized checks.
- Use waveform inspection to confirm handshake timing, not only final results.
- Synthesize early to see whether multiply infers DSP resources.

## References

- RISC-V unprivileged ISA, integer and M extension chapters: https://riscv.org/technical/specifications/
- AMD/Xilinx DSP48 documentation: https://docs.xilinx.com/
- Project F FPGA arithmetic articles: https://projectf.io/posts/