imple
e98b3694ab
Replace the first broad project sketch with more concrete hardware assumptions for implementation on the Arty A7 100T. Document the 50 MHz MMCM-derived clock, synchronous active-high reset after the board reset synchronizer, and a split instruction/data BRAM map with reset PC at 0x2000_0000. Update the UART layout to separate TX, RX, and status registers, and make the README/roadmap agree on the address ranges that firmware and the future linker script will use. Also split the M extension out of the combinational ALU into a dedicated multi-cycle unit with start/busy/done handshaking, describe BRAM latency and stall behavior in the single-cycle logical model, and add riscv-tests as the planned compliance check once GCC-generated programs are running.
65 lines
2.4 KiB
Markdown
65 lines
2.4 KiB
Markdown
# FPGA-Core
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Custom RV32IM RISC-V CPU core built from scratch in SystemVerilog.
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## Target
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- Board: Digilent Arty A7 100T (xc7a100tcsg324-1)
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- Toolchain: Vivado 2025.2 or later
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- Language: SystemVerilog
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- ISA: RV32IM + Zicsr + Zifencei + M-mode privileged (extending toward Linux)
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- Clock: 50 MHz (100 MHz xtal ÷ 2 via MMCM)
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## Architecture
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"Single-cycle" logical model (no pipeline registers), Harvard architecture
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(separate instruction/data BRAM). The combinational ALU and a multi-cycle M
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unit (DSP-based multiply, iterative divide) sit side by side; the datapath
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stalls on M-unit and BRAM accesses. Inter-stage signals are typed structs in
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`rv32_pkg.sv` — the same structs become pipeline registers when the core is
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pipelined later (Phase 12).
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## Memory Map
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| Address Range | Region |
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|---------------------------|----------------------------------------------|
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| `0x0000_0000–0x0FFF_FFFF` | reserved (SPI flash boot region, Phase 13) |
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| `0x1000_0000–0x1000_0FFF` | MMIO (UART; later: timer, PLIC) |
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| `0x2000_0000–0x2000_FFFF` | instruction BRAM (64 KB) |
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| `0x8000_0000–0x8000_FFFF` | data BRAM (64 KB) → DRAM in Phase 13 |
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Reset PC = `0x2000_0000`.
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UART registers (split layout):
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| Address | Access | Meaning |
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|---------------|--------|----------------------------------------------|
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| `0x1000_0000` | W | TX data — byte to send |
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| `0x1000_0004` | R | RX data — pops one byte from RX FIFO |
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| `0x1000_0008` | R | status — bit0 = `tx_busy`, bit1 = `rx_valid` |
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## Building
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Requires:
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- Vivado 2025.2 or later
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- RISC-V GCC toolchain — multilib `riscv64-unknown-elf-gcc` supporting
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`-march=rv32im_zicsr_zifencei -mabi=ilp32`
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- `riscv-tests` (for compliance verification from Phase 8.5)
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- Serial terminal (minicom/picocom/PuTTY) at 115200 8N1
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Open `FPGA-Core.xpr` in Vivado. Synthesis and implementation target the xc7a100tcsg324-1.
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## Roadmap
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See `ROADMAP.md` for the full phased build plan.
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## Current Phase
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Phase 0 — Architecture contract (package definitions + block diagram)
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## References
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- [RISC-V ISA Spec Vol 1 (Unprivileged)](https://riscv.org/technical/specifications/)
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- [RISC-V ISA Spec Vol 2 (Privileged)](https://riscv.org/technical/specifications/)
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- [Arty A7 Reference Manual](https://digilent.com/reference/programmable-logic/arty-a7/reference-manual)
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