imple
e98b3694ab
Replace the first broad project sketch with more concrete hardware assumptions for implementation on the Arty A7 100T. Document the 50 MHz MMCM-derived clock, synchronous active-high reset after the board reset synchronizer, and a split instruction/data BRAM map with reset PC at 0x2000_0000. Update the UART layout to separate TX, RX, and status registers, and make the README/roadmap agree on the address ranges that firmware and the future linker script will use. Also split the M extension out of the combinational ALU into a dedicated multi-cycle unit with start/busy/done handshaking, describe BRAM latency and stall behavior in the single-cycle logical model, and add riscv-tests as the planned compliance check once GCC-generated programs are running.
FPGA-Core
Custom RV32IM RISC-V CPU core built from scratch in SystemVerilog.
Target
- Board: Digilent Arty A7 100T (xc7a100tcsg324-1)
- Toolchain: Vivado 2025.2 or later
- Language: SystemVerilog
- ISA: RV32IM + Zicsr + Zifencei + M-mode privileged (extending toward Linux)
- Clock: 50 MHz (100 MHz xtal ÷ 2 via MMCM)
Architecture
"Single-cycle" logical model (no pipeline registers), Harvard architecture
(separate instruction/data BRAM). The combinational ALU and a multi-cycle M
unit (DSP-based multiply, iterative divide) sit side by side; the datapath
stalls on M-unit and BRAM accesses. Inter-stage signals are typed structs in
rv32_pkg.sv — the same structs become pipeline registers when the core is
pipelined later (Phase 12).
Memory Map
| Address Range | Region |
|---|---|
0x0000_0000–0x0FFF_FFFF |
reserved (SPI flash boot region, Phase 13) |
0x1000_0000–0x1000_0FFF |
MMIO (UART; later: timer, PLIC) |
0x2000_0000–0x2000_FFFF |
instruction BRAM (64 KB) |
0x8000_0000–0x8000_FFFF |
data BRAM (64 KB) → DRAM in Phase 13 |
Reset PC = 0x2000_0000.
UART registers (split layout):
| Address | Access | Meaning |
|---|---|---|
0x1000_0000 |
W | TX data — byte to send |
0x1000_0004 |
R | RX data — pops one byte from RX FIFO |
0x1000_0008 |
R | status — bit0 = tx_busy, bit1 = rx_valid |
Building
Requires:
- Vivado 2025.2 or later
- RISC-V GCC toolchain — multilib
riscv64-unknown-elf-gccsupporting-march=rv32im_zicsr_zifencei -mabi=ilp32 riscv-tests(for compliance verification from Phase 8.5)- Serial terminal (minicom/picocom/PuTTY) at 115200 8N1
Open FPGA-Core.xpr in Vivado. Synthesis and implementation target the xc7a100tcsg324-1.
Roadmap
See ROADMAP.md for the full phased build plan.
Current Phase
Phase 0 — Architecture contract (package definitions + block diagram)