imple
c7b19e8744
Establish the repository as a documentation-first plan for a custom SystemVerilog RISC-V CPU targeting the Digilent Arty A7 100T. Add the initial README, roadmap, and contributor guidance that define the starting RV32IM direction, Vivado/RISC-V toolchain expectations, basic SystemVerilog conventions, and the phased path from an architecture contract toward a Linux-capable SoC. This commit intentionally contains planning and interface direction only; RTL, firmware, testbenches, and Vivado project files are left for later phases.
50 lines
1.5 KiB
Markdown
50 lines
1.5 KiB
Markdown
# FPGA-Core
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Custom RV32IM RISC-V CPU core built from scratch in SystemVerilog.
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## Target
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- Board: Digilent Arty A7 100T
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- Toolchain: Vivado 2025.2.1
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- Language: SystemVerilog
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- ISA: RV32IM + Zicsr + Zifencei + M-mode privileged (extending toward Linux)
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## Architecture
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Single-cycle, non-pipelined, Harvard architecture (separate instruction/data BRAM).
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Designed for incremental extension — clean stage separation via typed structs so
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pipelining and new instructions can be added without structural rework.
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## Memory Map
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| Address Range | Peripheral |
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|-----------------------|--------------------|
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| 0x00000000-0x0FFFFFFF | BRAM (instr + data)|
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| 0x10000000 | UART TX/RX data |
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| 0x10000004 | UART status |
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(Will expand as peripherals are added)
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## Building
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Requires:
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- Vivado 2025.2.1
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- RISC-V GCC toolchain (`riscv64-unknown-elf-gcc`)
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- Serial terminal (minicom/picocom/PuTTY) at 115200 baud
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Open `FPGA-Core.xpr` in Vivado. Synthesis and implementation target the xc7a100tcsg324-1.
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## Roadmap
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See `ROADMAP.md` for the full phased build plan.
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## Current Phase
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Phase 0 — Architecture contract (package definitions + block diagram)
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## References
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- [RISC-V ISA Spec Vol 1 (Unprivileged)](https://riscv.org/technical/specifications/)
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- [RISC-V ISA Spec Vol 2 (Privileged)](https://riscv.org/technical/specifications/)
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- [Arty A7 Reference Manual](https://digilent.com/reference/programmable-logic/arty-a7/reference-manual)
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