# FPGA-Core

Custom RV32IM RISC-V CPU core built from scratch in SystemVerilog.

## Target

- Board: Digilent Arty A7 100T
- Toolchain: Vivado 2025.2.1
- Language: SystemVerilog
- ISA: RV32IM + Zicsr + Zifencei + M-mode privileged (extending toward Linux)

## Architecture

Single-cycle, non-pipelined, Harvard architecture (separate instruction/data BRAM).
Designed for incremental extension — clean stage separation via typed structs so
pipelining and new instructions can be added without structural rework.

## Memory Map

| Address Range         | Peripheral         |
|-----------------------|--------------------|
| 0x00000000-0x0FFFFFFF | BRAM (instr + data)|
| 0x10000000            | UART TX/RX data    |
| 0x10000004            | UART status        |

(Will expand as peripherals are added)

## Building

Requires:
- Vivado 2025.2.1
- RISC-V GCC toolchain (`riscv64-unknown-elf-gcc`)
- Serial terminal (minicom/picocom/PuTTY) at 115200 baud

Open `FPGA-Core.xpr` in Vivado. Synthesis and implementation target the xc7a100tcsg324-1.

## Roadmap

See `ROADMAP.md` for the full phased build plan.

## Current Phase

Phase 0 — Architecture contract (package definitions + block diagram)

## References

- [RISC-V ISA Spec Vol 1 (Unprivileged)](https://riscv.org/technical/specifications/)
- [RISC-V ISA Spec Vol 2 (Privileged)](https://riscv.org/technical/specifications/)
- [Arty A7 Reference Manual](https://digilent.com/reference/programmable-logic/arty-a7/reference-manual)