53 lines
1.9 KiB
Markdown
53 lines
1.9 KiB
Markdown
# Phase 16 - Linux Boot Contract
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## Context
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Linux does not start from reset like bare-metal firmware. It expects a specific entry
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state, memory layout, device tree, and usually firmware services.
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## Goals
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- Define the exact kernel entry ABI.
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- Provide a device tree describing the SoC.
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- Choose direct M-mode Linux or OpenSBI + S-mode Linux.
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## New Concepts
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- Device tree: data structure describing hardware to the kernel.
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- DTB: compiled binary form of a device tree source.
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- SBI: Supervisor Binary Interface, firmware API used by S-mode kernels.
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- OpenSBI: common RISC-V machine-mode firmware implementation.
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- Hart: RISC-V hardware thread, roughly a CPU core/thread.
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## How To Think About It
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This phase is about removing ambiguity before kernel bring-up. If the boot contract is
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wrong, Linux often just hangs early with little output.
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## Learning Tasks
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- Read the RISC-V Linux boot protocol and list required register state.
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- Draft a device tree matching your memory map and interrupt topology.
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- Use the modern CPU ISA properties: `riscv,isa-base = "rv32i"` and
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`riscv,isa-extensions = "i", "m", "a", "zicsr", "zifencei"`. Keep the legacy
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`riscv,isa = "rv32ima_zicsr_zifencei"` string only as a compatibility fallback.
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- Decide whether the first Linux attempt uses direct M-mode or OpenSBI.
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## Pitfalls
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- Passing the wrong DTB address in `a1`.
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- Loading the kernel at the wrong alignment.
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- Claiming device-tree compatibility with hardware you did not implement.
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## Tooling And Testing
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- Validate DTS with `dtc`.
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- Keep early console strategy simple and documented.
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- Build small firmware checks that print boot parameters before jumping to Linux.
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## References
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- RISC-V Linux boot protocol: https://docs.kernel.org/arch/riscv/boot.html
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- RISC-V device-tree CPU bindings: https://www.kernel.org/doc/Documentation/devicetree/bindings/riscv/cpus.yaml
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- OpenSBI: https://github.com/riscv-software-src/opensbi
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