FPGA-Core/Tutorial

FPGA-Core Tutorial

This tutorial tree follows ROADMAP.md. Each phase and subphase has a learning note with the same structure:

• Context
• Goals
• New Concepts
• How To Think About It
• Learning Tasks
• Pitfalls
• Tooling And Testing
• References

The notes assume strong Linux/systems experience and beginner-to-intermediate FPGA and digital-design experience. They intentionally avoid giving implementation code. The goal is to explain what to learn, what to verify, and what mistakes to avoid.

Phase Index

• Phase 0 - Architecture Contract
• Phase 1 - ALU + M Unit
• Phase 2 - Register File
• Phase 3 - Decoder
• Phase 4 - First CPU
• Phase 5 - Branches And Jumps
• Phase 6 - Load/Store
• Phase 7 - Memory-Mapped UART
• Phase 8 - GCC Toolchain Integration
• Phase 9 - CSRs + M-Mode Traps
• Phase 10 - Timer
• Phase 11 - Interrupt Controller
• Phase 12 - Atomics
• Phase 13 - Pipeline
• Phase 14 - SPI Flash + DRAM
• Phase 15 - M/S/U + Sv32
• Phase 16 - Linux Boot Contract
• Phase 17 - Linux