Phase 14 - SPI Flash Boot + DRAM

Context

BRAM is small and initialized by the FPGA bitstream. A Linux-capable system needs persistent boot storage and much larger RAM, so this phase adds flash boot and DDR3L.

Goals

Boot from on-board SPI flash.
Integrate DDR3L through the Xilinx MIG IP.
Move executable images into DRAM and run from there.

New Concepts

SPI flash: serial nonvolatile storage on the board.
DRAM: external dynamic memory requiring a controller and refresh.
MIG: Xilinx Memory Interface Generator IP for DDR memory controllers.
Bootloader: small program that prepares memory and jumps to a larger image.
Arbiter: logic choosing which bus master accesses shared memory.

How To Think About It

This is the first major SoC integration phase. External memory is not a simple array: latency varies, calibration matters, and reset sequencing becomes important.

The concrete map follows the roadmap: the 16 MB on-board SPI flash is mapped at 0x0000_0000-0x00FF_FFFF inside the reserved boot aperture, and the 256 MB DDR3L DRAM replaces data BRAM at 0x8000_0000-0x8FFF_FFFF.

Learning Tasks

Understand the Arty A7 memory devices and the fixed address ranges above.
Draw boot flow from reset to flash fetch to DRAM copy to jump.
Decide how I-bus and D-bus arbitrate for DRAM.

Pitfalls

Assuming DRAM is ready immediately after FPGA reset.
Ignoring MIG clocking and reset requirements.
Mixing boot ROM, flash aperture, and DRAM addresses without a clear map.

Tooling And Testing

Validate DRAM with a standalone memory test before CPU boot.
Use ILA around MIG app interface and bus arbiter.
Keep a tiny BRAM-resident fallback test path while debugging flash/DRAM.

References

Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
AMD/Xilinx MIG documentation: https://docs.xilinx.com/
DDR3 SDRAM background: https://en.wikipedia.org/wiki/DDR3_SDRAM

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