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Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
1.5 KiB
1.5 KiB
Phase 7.1 - UART TX Module
Context
The TX module serializes bytes into start bit, data bits, and stop bit at a fixed baud rate. It is a small timing-driven FSM.
Goals
- Build a standalone transmitter.
- Learn baud-rate timing from the 50 MHz system clock.
- Verify busy/send behavior before CPU integration.
New Concepts
- Baud rate: symbols per second on the serial line.
- Start bit: low bit marking beginning of a frame.
- Stop bit: high bit marking end of a frame.
- Bit timer: counter that holds each serial bit for the right number of clocks.
How To Think About It
UART TX is a deterministic shift-and-timer machine. The hard part is not data structure; it is exact timing and clean handoff from "send byte" to "busy."
Learning Tasks
- Compute clocks per bit at 50 MHz and 115200 baud.
- Draw TX line waveform for one byte.
- Decide when
busyasserts and deasserts.
Pitfalls
- Off-by-one errors in the bit timer.
- Accepting a new byte before the previous frame has completed.
- Forgetting idle line is high.
Tooling And Testing
- Simulate one byte and inspect the waveform.
- Test back-to-back bytes.
- On hardware, send a fixed message before involving the CPU.
References
- Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
- UART framing overview: https://en.wikipedia.org/wiki/Universal_asynchronous_receiver-transmitter
- Nandland UART tutorial: https://nandland.com/uart-serial-port-module/