# Phase 7.1 - UART TX Module

## Context

The TX module serializes bytes into start bit, data bits, and stop bit at a fixed baud
rate. It is a small timing-driven FSM.

## Goals

- Build a standalone transmitter.
- Learn baud-rate timing from the 50 MHz system clock.
- Verify busy/send behavior before CPU integration.

## New Concepts

- Baud rate: symbols per second on the serial line.
- Start bit: low bit marking beginning of a frame.
- Stop bit: high bit marking end of a frame.
- Bit timer: counter that holds each serial bit for the right number of clocks.

## How To Think About It

UART TX is a deterministic shift-and-timer machine. The hard part is not data structure;
it is exact timing and clean handoff from "send byte" to "busy."

## Learning Tasks

- Compute clocks per bit at 50 MHz and 115200 baud.
- Draw TX line waveform for one byte.
- Decide when `busy` asserts and deasserts.

## Pitfalls

- Off-by-one errors in the bit timer.
- Accepting a new byte before the previous frame has completed.
- Forgetting idle line is high.

## Tooling And Testing

- Simulate one byte and inspect the waveform.
- Test back-to-back bytes.
- On hardware, send a fixed message before involving the CPU.

## References

- Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
- UART framing overview: https://en.wikipedia.org/wiki/Universal_asynchronous_receiver-transmitter
- Nandland UART tutorial: https://nandland.com/uart-serial-port-module/