imple
b008b37d49
Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
50 lines
1.5 KiB
Markdown
50 lines
1.5 KiB
Markdown
# Phase 5 - Branches And Jumps
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## Context
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This phase adds control flow. The CPU stops being a straight-line executor and gains
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loops, conditionals, function calls, and returns.
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## Goals
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- Implement conditional branches.
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- Implement `jal` and `jalr`.
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- Learn PC selection and control-transfer testing.
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## New Concepts
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- Branch target: destination address for a taken branch.
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- Fall-through: next sequential PC, usually PC + 4.
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- Link register: register receiving return address for calls.
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- Control hazard: later pipeline issue where fetched instructions may be wrong.
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## How To Think About It
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Control flow is just PC update logic plus optional register writeback. Keep the
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comparison, target calculation, and PC selection clearly separated.
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## Learning Tasks
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- Hand-compute branch and jump targets from instruction immediates.
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- Trace a simple loop and count taken versus not-taken branches.
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- Understand why `jalr` clears bit 0 of the target address.
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## Pitfalls
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- Off-by-four errors between current PC and next PC.
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- Using unsigned comparison for signed branches.
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- Forgetting that `jal`/`jalr` write PC + 4 to `rd`.
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## Tooling And Testing
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- Test both taken and not-taken paths for every branch type.
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- Use short loops with known iteration counts.
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- Probe PC source selection in simulation and ILA.
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## References
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- RISC-V branch and jump semantics: https://riscv.org/technical/specifications/
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- RISC-V assembly examples: https://github.com/riscv-non-isa/riscv-asm-manual
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- Computer architecture control flow overview: https://www.nand2tetris.org/
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