49 lines
1.7 KiB
Markdown
49 lines
1.7 KiB
Markdown
# Phase 1.1 - Combinational ALU
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## Context
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The ALU is the easiest place to learn the difference between software expressions and
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hardware behavior. Every operation is hardware that exists in parallel behind a selector.
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## Goals
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- Implement RV32I arithmetic, logic, comparison, and shift operations.
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- Verify every operation independently.
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- Learn how signedness works in SystemVerilog.
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## New Concepts
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- Signedness: whether bits are interpreted as two's-complement signed values.
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- Shift amount: RISC-V uses only the low 5 bits for RV32 shifts.
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- Overflow: addition overflow is usually ignored for RV32I arithmetic results.
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- Combinational completeness: every output is assigned for every input path.
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## How To Think About It
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The same 32-bit vector can be signed or unsigned depending on the operation. Make the
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interpretation explicit in your design notes and tests.
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## Learning Tasks
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- Make a table of each ALU op, its operands, and expected result semantics.
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- Hand-check edge cases such as `0`, `-1`, `INT_MIN`, and `INT_MAX`.
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- Compare arithmetic right shift with logical right shift.
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## Pitfalls
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- Accidentally creating latches by not assigning outputs in every case.
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- Using host-language intuition for signed comparisons.
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- Forgetting that `slt` and `sltu` are different instructions.
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## Tooling And Testing
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- Use a small self-checking testbench before opening a waveform.
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- Add waveform inspection for failing tests only; do not debug by staring first.
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- Include cases where signed and unsigned answers differ.
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## References
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- RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
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- SystemVerilog types, operators, and expressions: https://systemverilog.dev/2.html
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- Verilator warnings guide: https://verilator.org/guide/latest/warnings.html
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