49 lines
1.9 KiB
Markdown
49 lines
1.9 KiB
Markdown
# Phase 0.1 - SystemVerilog Package
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## Context
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The package is the shared type layer for the project. It prevents every module from
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inventing its own encodings and signal names.
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## Goals
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- Define enums for ALU operations, branch types, memory sizes, and instruction classes.
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- Define structs for stage outputs and memory request/response payloads.
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- Make later extension possible without rewriting every module boundary.
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## New Concepts
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- Packed struct: a struct with a defined bit layout, suitable for wires and registers.
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- Typedef: named type alias used to make RTL readable.
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- Import: SystemVerilog mechanism for using package definitions in modules.
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- Encoding: the bit pattern used for enum values in synthesized hardware.
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## How To Think About It
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The package is not a dumping ground. It should contain stable contracts and shared
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definitions. If a signal is private to one module, keep it private.
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## Learning Tasks
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- List every planned stage boundary and define what information must cross it.
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- Separate architectural information, such as register addresses, from local control.
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- Decide naming conventions before writing dependent modules.
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## Pitfalls
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- Relying on implicit enum widths and later discovering mismatched synthesis behavior.
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- Putting handshake `ready` signals inside one-way payload structs.
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- Adding fields "just in case" without knowing who drives or consumes them.
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## Tooling And Testing
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- Compile the package alone and then with one tiny importing module.
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- Inspect elaboration messages; type errors here are usually design-contract errors.
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- Keep comments on fields short but precise about direction and ownership.
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## References
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- SystemVerilog packages and typedefs: https://www.chipverify.com/systemverilog/systemverilog-package
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- LowRISC SystemVerilog style: https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md
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- RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
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