20 lines
721 B
Markdown
20 lines
721 B
Markdown
# FPGA/vivado/
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The Vivado project workspace. The committed source of truth is
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`create_project.tcl`; the project file (`FPGA-Core.xpr`) and all of Vivado's
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generated state (`*.runs/`, `*.cache/`, `*.hw/`, `*.sim/`, `*.ip_user_files/`,
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`*.gen/`, `*.srcs/`) are git-ignored — `.xpr` files embed machine-specific
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paths and are regenerated locally.
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RTL and testbench files are added to the project as **references** to
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`../rtl/...` / `../tb/...` so the actual source of truth stays in version
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control, not inside the project file.
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To generate the project, run from the repo root:
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```sh
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vivado -mode batch -source FPGA/vivado/create_project.tcl
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```
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Then open the resulting `FPGA/vivado/FPGA-Core.xpr` in the Vivado GUI.
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