imple
b008b37d49
Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
50 lines
1.7 KiB
Markdown
50 lines
1.7 KiB
Markdown
# Phase 1.2 - Multi-Cycle M Unit
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## Context
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Multiply and divide belong in a dedicated unit because their timing and control behavior
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are different from simple ALU operations.
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## Goals
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- Implement multiply, high-half multiply, divide, and remainder behavior.
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- Learn multi-cycle control using `start`, `busy`, and `done`.
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- Verify all RISC-V-defined edge cases.
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## New Concepts
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- High-half multiply: result uses bits 63:32 of a 64-bit product.
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- Iterative divider: divider that computes one bit or small group of bits per cycle.
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- FSM: finite-state machine controlling multi-cycle behavior.
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- Latency: number of cycles from request to result.
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## How To Think About It
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Treat the M unit like a tiny asynchronous service from the core's perspective. The core
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asks for work, waits, and resumes only when the result is stable.
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## Learning Tasks
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- Write down the expected result for divide-by-zero and signed overflow.
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- Draw state transitions for idle, multiply, divide, done, and back-to-back requests.
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- Decide when inputs are latched and when outputs are valid.
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## Pitfalls
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- Allowing operands to change while an operation is in flight.
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- Returning C-language division behavior instead of RISC-V behavior.
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- Forgetting `mulhsu`, which mixes signed and unsigned operands.
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## Tooling And Testing
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- Use long waveform windows to inspect division progress.
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- Include tests that assert `start` while `busy` and confirm the intended behavior.
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- Synthesize to confirm multiply maps to DSPs and divide maps to logic/state.
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## References
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- RISC-V M extension spec: https://riscv.org/technical/specifications/
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- Project F multiplication: https://projectf.io/posts/multiplication-fpga-dsps/
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- Project F division: https://projectf.io/posts/division-in-verilog/
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