52 lines
1.8 KiB
Markdown
52 lines
1.8 KiB
Markdown
# Phase 14 - Interrupt Controller
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## Context
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After the timer, the system needs a way to manage external interrupt sources such as UART
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RX. A PLIC-like controller arbitrates and presents external interrupts to the CPU.
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## Goals
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- Build a minimal interrupt controller.
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- Connect UART RX as an interrupt source.
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- Learn interrupt priority, enable, pending, claim, and complete concepts.
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## New Concepts
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- PLIC: Platform-Level Interrupt Controller used by many RISC-V systems.
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- Interrupt priority: ordering among pending interrupt sources.
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- Claim: software reads which interrupt it should service.
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- Complete: software tells the controller an interrupt has been handled.
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- Edge/level interrupt: whether an event is a pulse or held condition.
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## How To Think About It
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An interrupt controller is hardware/software coordination. The device requests service,
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the controller prioritizes it, the CPU traps, and software acknowledges the right places
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in the right order.
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## Learning Tasks
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- Draw interrupt flow from UART RX byte to trap handler.
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- Decide whether UART interrupt is level-sensitive or edge-sensitive.
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- Understand claim/complete even if your first controller is simplified.
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## Pitfalls
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- Losing an interrupt event because it is only a one-cycle pulse.
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- Clearing the device before software can observe why it interrupted.
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- Taking an interrupt repeatedly because pending state is never cleared.
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## Tooling And Testing
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- Start with one interrupt source before adding priority.
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- Test masked, unmasked, pending, claim, and complete behavior.
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- Use ILA on interrupt request, pending, CPU external interrupt, and trap entry.
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## References
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- RISC-V PLIC specification: https://github.com/riscv/riscv-plic-spec
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- RISC-V privileged architecture spec: https://riscv.org/technical/specifications/
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- Linux interrupt concepts: https://docs.kernel.org/core-api/genericirq.html
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