49 lines
1.6 KiB
Markdown
49 lines
1.6 KiB
Markdown
# Phase 13 - Timer
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## Context
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A timer provides a predictable interrupt source. Operating systems need timers for
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scheduling, timeouts, and delays.
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## Goals
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- Implement a free-running machine timer counter.
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- Implement compare register behavior.
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- Generate and handle timer interrupts through the trap path.
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## New Concepts
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- `mtime`: monotonically increasing machine timer counter.
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- `mtimecmp`: compare value that triggers a timer interrupt when reached.
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- Interrupt: asynchronous trap caused by external or timer event.
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- Pending bit: CSR bit indicating an interrupt source is waiting.
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## How To Think About It
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Timer hardware is simple; correct interrupt integration is the real lesson. You must
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coordinate compare logic, pending state, enable bits, global interrupt enable, and trap entry.
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## Learning Tasks
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- Draw how `mtime`, `mtimecmp`, `mip`, and `mie` relate.
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- Decide how software reads/writes a 64-bit timer from a 32-bit core.
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- Trace a timer interrupt from compare match to handler entry.
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## Pitfalls
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- Generating level interrupts that never clear.
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- Mishandling 64-bit register access from RV32 software.
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- Taking interrupts while already in an unsafe state.
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## Tooling And Testing
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- Simulate with small compare values so tests finish quickly.
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- Test enabling, disabling, pending, and clearing behavior separately.
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- Add waveform probes for `mtime`, compare result, pending bit, and trap entry.
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## References
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- RISC-V privileged architecture spec: https://riscv.org/technical/specifications/
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- RISC-V ACLINT specification: https://github.com/riscvarchive/riscv-aclint
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- Linux timekeeping background: https://docs.kernel.org/timers/
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