imple
b008b37d49
Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
50 lines
1.6 KiB
Markdown
50 lines
1.6 KiB
Markdown
# Phase 7.3 - Bus Decoder + MMIO
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## Context
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The D-bus now routes requests to either RAM or UART registers. This is the first small
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SoC-style memory map.
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## Goals
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- Decode address ranges for RAM and UART.
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- Implement UART TX, RX, and status registers.
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- Preserve the D-bus handshake contract.
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## New Concepts
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- Address map: assignment of address ranges to memory or devices.
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- Register side effect: read or write that changes device state.
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- Unmapped access: address with no valid target, later an access fault.
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- Peripheral slave: bus endpoint that responds to device register accesses.
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## How To Think About It
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MMIO registers are a hardware/software ABI. Once firmware depends on them, changing
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semantics becomes painful. Document behavior precisely.
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## Learning Tasks
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- Write a register table with access type and side effects.
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- Decide read behavior for write-only registers and write behavior for read-only registers.
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- Trace a store to UART TX through the D-bus decoder.
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## Pitfalls
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- Having two slaves respond to the same address.
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- Letting no slave respond and hanging the bus forever.
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- Making status bits unclear or inverted relative to software expectations.
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## Tooling And Testing
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- Unit-test the decoder separately from UART timing.
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- Use ILA probes on selected slave, request, response, and UART status.
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- Test unmapped access behavior once trap support exists.
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## References
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- OSDev MMIO overview: https://wiki.osdev.org/Memory_Mapped_Registers_in_C/C%2B%2B
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- RISC-V privileged spec for access faults later: https://riscv.org/technical/specifications/
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- Wishbone bus spec: https://cdn.opencores.org/downloads/wbspec_b4.pdf
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