imple
b008b37d49
Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
1.6 KiB
1.6 KiB
Phase 4.2 - ILA Verification On FPGA
Context
ILA lets you capture internal FPGA signals during real hardware execution. This is the first serious hardware-debug milestone for the integrated CPU.
Goals
- Learn how to select useful ILA probes.
- Capture PC, instruction, writeback, and state transitions.
- Compare hardware behavior to simulation.
New Concepts
- ILA: Integrated Logic Analyzer, on-chip waveform capture over JTAG.
- Trigger: condition that starts or centers a capture.
- Sample depth: number of cycles stored in on-chip debug memory.
- Probe preservation: keeping signals from being optimized away.
How To Think About It
ILA is an oscilloscope for internal logic. Use it to answer a specific question, not to record everything. Every extra probe has cost.
Learning Tasks
- Choose a trigger such as PC reaching the last instruction.
- Decide which signals prove correct instruction retirement.
- Compare one hardware trace with the simulator trace for the same program.
Pitfalls
- Capturing too few cycles before/after the trigger.
- Debugging a different bitstream than the source you are reading.
- Assuming ILA changes nothing; debug IP consumes resources and can affect timing.
Tooling And Testing
- Archive the program image, bitstream, and source commit used for hardware tests.
- Use
dont_touchsparingly and only on debug-critical nets. - Check timing again after inserting ILA.
References
- Vivado ILA documentation: https://docs.xilinx.com/
- Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
- AMD/Xilinx debug methodology: https://docs.xilinx.com/