Files

T

imple b008b37d49 Add phase-by-phase tutorial notes

Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up.
Each phase and subphase gets a short learning note with consistent sections for
context, goals, new concepts, mental model, learning tasks, pitfalls, tooling,
testing, and references.

The tutorial material is intentionally explanatory rather than implementation
code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V,
firmware, and Linux bring-up context to approach each roadmap phase without
turning the notes into copy-paste RTL.

2026-04-28 12:11:23 +02:00

1.5 KiB

Raw Blame History

Phase 5 - Branches And Jumps

Context

This phase adds control flow. The CPU stops being a straight-line executor and gains loops, conditionals, function calls, and returns.

Goals

Implement conditional branches.
Implement jal and jalr.
Learn PC selection and control-transfer testing.

New Concepts

Branch target: destination address for a taken branch.
Fall-through: next sequential PC, usually PC + 4.
Link register: register receiving return address for calls.
Control hazard: later pipeline issue where fetched instructions may be wrong.

How To Think About It

Control flow is just PC update logic plus optional register writeback. Keep the comparison, target calculation, and PC selection clearly separated.

Learning Tasks

Hand-compute branch and jump targets from instruction immediates.
Trace a simple loop and count taken versus not-taken branches.
Understand why jalr clears bit 0 of the target address.

Pitfalls

Off-by-four errors between current PC and next PC.
Using unsigned comparison for signed branches.
Forgetting that jal/jalr write PC + 4 to rd.

Tooling And Testing

Test both taken and not-taken paths for every branch type.
Use short loops with known iteration counts.
Probe PC source selection in simulation and ILA.

References

RISC-V branch and jump semantics: https://riscv.org/technical/specifications/
RISC-V assembly examples: https://github.com/riscv-non-isa/riscv-asm-manual
Computer architecture control flow overview: https://www.nand2tetris.org/

1.5 KiB Raw Blame History