imple
b008b37d49
Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
50 lines
1.7 KiB
Markdown
50 lines
1.7 KiB
Markdown
# Phase 4.1 - Fetch + Datapath Integration
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## Context
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This subphase builds the first CPU loop: fetch an instruction, decode it, execute it,
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write back a result, and advance PC.
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## Goals
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- Integrate instruction BRAM at `0x2000_0000`.
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- Execute straight-line arithmetic and M-extension operations.
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- Learn stall control around BRAM and the M unit.
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## New Concepts
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- Reset PC: address where execution begins after reset.
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- FSM state: named control state such as fetch, execute, wait, writeback.
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- Instruction retirement: point where an instruction's architectural effects are complete.
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- Stall: holding PC/state while waiting for a dependency.
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## How To Think About It
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The CPU is a protocol participant with its memories and M unit. Correct sequencing matters
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more than minimizing cycles.
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## Learning Tasks
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- Write a cycle-by-cycle timeline for a simple `addi` instruction.
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- Write a cycle-by-cycle timeline for a multiply/divide instruction.
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- Decide what happens on illegal instruction before Phase 9 traps exist.
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## Pitfalls
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- Double-executing an instruction because PC or state advances at the wrong time.
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- Starting the M unit repeatedly while waiting for it to finish.
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- Losing the destination register number while a multi-cycle op is in flight.
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## Tooling And Testing
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- Use a testbench that stops after a fixed halt condition or maximum cycle count.
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- Compare final register state and intermediate writeback events.
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- Inspect PC, instruction, state, register write enable, and writeback data in waveforms.
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## References
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- RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
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- Vivado simulation documentation: https://docs.xilinx.com/
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- Project F memory initialization: https://projectf.io/posts/initialize-memory-in-verilog/
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