imple
b008b37d49
Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
50 lines
1.6 KiB
Markdown
50 lines
1.6 KiB
Markdown
# Phase 2.1 - Register File Module
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## Context
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This subphase turns the architectural register model into clocked hardware with two
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combinational reads and one synchronous write.
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## Goals
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- Implement 32 registers of 32 bits.
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- Enforce `x0` semantics.
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- Verify read, write, and collision behavior.
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## New Concepts
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- Synchronous write: state changes only at the active clock edge.
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- Combinational read: output changes when the address changes.
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- Read-after-write: reading an address in the same cycle it is written.
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- Bypass/forwarding: returning newly written data without waiting for storage update.
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## How To Think About It
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Choose behavior deliberately. A simple non-pipelined core can tolerate many choices, but
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tests and later pipeline work become easier if the behavior is documented.
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## Learning Tasks
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- Write a truth table for `write_enable`, `rd`, `rs1`, and `rs2` interactions.
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- Decide how reset affects registers, if at all.
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- Confirm whether the register file should initialize to zero for simulation clarity.
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## Pitfalls
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- Resetting a large register file unnecessarily in hardware.
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- Making simulation behavior differ from synthesis behavior.
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- Forgetting that reads from `x0` must ignore any stored value.
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## Tooling And Testing
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- Use assertions for `x0` if your simulator supports them.
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- Run repeated randomized write/read sequences.
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- Inspect synthesis resource use; this may infer LUT RAM or flip-flops.
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## References
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- RISC-V ABI register names: https://riscv.org/technical/specifications/
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- SystemVerilog always_ff guidance: https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md
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- Vivado synthesis guide: https://docs.xilinx.com/
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