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Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
1.6 KiB
1.6 KiB
Phase 8.5 - riscv-tests Compliance
Context
Official instruction tests catch ISA bugs that ad hoc tests miss. Run them before adding trap, interrupt, and privilege complexity.
Goals
- Build and run
rv32ui-p-*andrv32um-p-*. - Create a simulation harness that loads test programs.
- Establish regression coverage for later phases.
New Concepts
- Compliance test: focused program checking architectural behavior.
- Harness: wrapper that provides memory, stop condition, and pass/fail reporting.
- Signature region: memory region where tests record results.
- Regression: test suite run repeatedly to catch breakage.
How To Think About It
Do not treat compliance tests as optional polish. They are how you avoid stacking new features on top of unknown ISA bugs.
Learning Tasks
- Understand how a riscv-test indicates pass/fail.
- Learn how ELF sections map into your BRAM model.
- Categorize failures by decode, execute, memory, or control-flow likely cause.
Pitfalls
- Running tests with the wrong ISA target.
- Assuming the test harness memory layout matches your hardware automatically.
- Ignoring one failing test because normal firmware seems to work.
Tooling And Testing
- Automate running all tests once the harness exists.
- Keep failing waveforms short and reproducible.
- Re-run the suite after every meaningful datapath change.
References
- riscv-tests repository: https://github.com/riscv-software-src/riscv-tests
- RISC-V architectural tests: https://github.com/riscv-non-isa/riscv-arch-test
- RISC-V unprivileged ISA: https://riscv.org/technical/specifications/