Phase 1.1 - Combinational ALU

Context

The ALU is the easiest place to learn the difference between software expressions and hardware behavior. Every operation is hardware that exists in parallel behind a selector.

Goals

Implement RV32I arithmetic, logic, comparison, and shift operations.
Verify every operation independently.
Learn how signedness works in SystemVerilog.

New Concepts

Signedness: whether bits are interpreted as two's-complement signed values.
Shift amount: RISC-V uses only the low 5 bits for RV32 shifts.
Overflow: addition overflow is usually ignored for RV32I arithmetic results.
Combinational completeness: every output is assigned for every input path.

How To Think About It

The same 32-bit vector can be signed or unsigned depending on the operation. Make the interpretation explicit in your design notes and tests.

Learning Tasks

Make a table of each ALU op, its operands, and expected result semantics.
Hand-check edge cases such as 0, -1, INT_MIN, and INT_MAX.
Compare arithmetic right shift with logical right shift.

Pitfalls

Accidentally creating latches by not assigning outputs in every case.
Using host-language intuition for signed comparisons.
Forgetting that slt and sltu are different instructions.

Tooling And Testing

Use a small self-checking testbench before opening a waveform.
Add waveform inspection for failing tests only; do not debug by staring first.
Include cases where signed and unsigned answers differ.

References

RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
SystemVerilog types, operators, and expressions: https://systemverilog.dev/2.html
Verilator warnings guide: https://verilator.org/guide/latest/warnings.html

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