imple
c1ffb0ee41
Drop the Current Phase section because it is a progress marker that would go stale or create noisy commits as the roadmap advances. Add a minimal .gitignore for local Codex state only, keeping broader ignore rules out until the repo actually needs them.
64 lines
2.6 KiB
Markdown
64 lines
2.6 KiB
Markdown
# FPGA-Core
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Custom RISC-V CPU core built from scratch in SystemVerilog. Starts as RV32IM,
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grows to RV32IMA + Sv32 + M/S/U privilege en route to booting Linux.
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## Target
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- Board: Digilent Arty A7 100T (xc7a100tcsg324-1)
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- Toolchain: Vivado 2025.2 or later
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- Language: SystemVerilog
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- ISA: end target **RV32IMA + Zicsr + Zifencei + M/S/U privilege + Sv32**
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(Linux-capable). Built incrementally — see `ROADMAP.md`.
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- Clock: 50 MHz (100 MHz xtal ÷ 2 via MMCM)
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## Architecture
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"Single-cycle" logical model (no pipeline registers), Harvard architecture
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(separate instruction/data BRAM). The combinational ALU and a multi-cycle M
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unit (DSP-based multiply, iterative divide) sit side by side; the datapath
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stalls on M-unit and BRAM accesses. Inter-stage signals are typed structs in
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`rv32_pkg.sv` — the same structs become pipeline registers when the core is
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pipelined later (Phase 13, optional).
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## Memory Map
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| Address Range | Region |
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|---------------------------|----------------------------------------------|
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| `0x0000_0000–0x0FFF_FFFF` | reserved boot aperture (Phase 14: 16 MB SPI flash at low end) |
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| `0x1000_0000–0x1000_0FFF` | MMIO (UART; later: timer, PLIC) |
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| `0x2000_0000–0x2000_FFFF` | instruction BRAM (64 KB) |
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| `0x8000_0000–0x8000_FFFF` | data BRAM (64 KB) → DRAM in Phase 14 |
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Reset PC = `0x2000_0000`.
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UART registers (split layout):
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| Address | Access | Meaning |
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|---------------|--------|----------------------------------------------|
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| `0x1000_0000` | W | TX data — byte to send |
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| `0x1000_0004` | R | RX data — pops one byte from RX FIFO |
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| `0x1000_0008` | R | status — bit0 = `tx_busy`, bit1 = `rx_valid` |
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## Building
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Requires:
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- Vivado 2025.2 or later
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- RISC-V GCC toolchain — multilib `riscv64-unknown-elf-gcc`. March string
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evolves with the implementation: `rv32im` (Phase 8) →
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`rv32im_zicsr_zifencei` (Phase 9) → `rv32ima_zicsr_zifencei` (Phase 12).
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- `riscv-tests` (for compliance verification from Phase 8.5)
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- Serial terminal (minicom/picocom/PuTTY) at 115200 8N1
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Open `FPGA-Core.xpr` in Vivado. Synthesis and implementation target the xc7a100tcsg324-1.
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## Roadmap
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See `ROADMAP.md` for the full phased build plan.
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## References
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- [RISC-V ISA Spec Vol 1 (Unprivileged)](https://riscv.org/technical/specifications/)
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- [RISC-V ISA Spec Vol 2 (Privileged)](https://riscv.org/technical/specifications/)
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- [Arty A7 Reference Manual](https://digilent.com/reference/programmable-logic/arty-a7/reference-manual)
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