imple
8edfc86027
Convert the memory-bus guidance from a loose list of request/response fields into packed mem_req_t and mem_rsp_t payload structs carried by separate valid/ready handshakes. Spell out that the same channel shape is instantiated independently for the instruction bus and data bus so the design remains Harvard at the bus level while still sharing a single contract. Clarify fault ownership before RTL exists: slaves only raise rsp.err for access faults they can own, the LSU detects misaligned loads/stores before issuing a D-bus request, the decoder owns illegal instructions and ebreak/ecall decode events, and the future MMU owns page faults before translated requests reach the bus. Update the roadmap to use the structured bus field names, correct the misalignment tests and GCC illegal-instruction explanation, and prefer modern RISC-V device-tree ISA properties with an optional legacy riscv,isa string for older kernels.
FPGA-Core
Custom RISC-V CPU core built from scratch in SystemVerilog. Starts as RV32IM, grows to RV32IMA + Sv32 + M/S/U privilege en route to booting Linux.
Target
- Board: Digilent Arty A7 100T (xc7a100tcsg324-1)
- Toolchain: Vivado 2025.2 or later
- Language: SystemVerilog
- ISA: end target RV32IMA + Zicsr + Zifencei + M/S/U privilege + Sv32
(Linux-capable). Built incrementally — see
ROADMAP.md. - Clock: 50 MHz (100 MHz xtal ÷ 2 via MMCM)
Architecture
"Single-cycle" logical model (no pipeline registers), Harvard architecture
(separate instruction/data BRAM). The combinational ALU and a multi-cycle M
unit (DSP-based multiply, iterative divide) sit side by side; the datapath
stalls on M-unit and BRAM accesses. Inter-stage signals are typed structs in
rv32_pkg.sv — the same structs become pipeline registers when the core is
pipelined later (Phase 13, optional).
Memory Map
| Address Range | Region |
|---|---|
0x0000_0000–0x0FFF_FFFF |
reserved boot aperture (Phase 14: 16 MB SPI flash at low end) |
0x1000_0000–0x1000_0FFF |
MMIO (UART; later: timer, PLIC) |
0x2000_0000–0x2000_FFFF |
instruction BRAM (64 KB) |
0x8000_0000–0x8000_FFFF |
data BRAM (64 KB) → DRAM in Phase 14 |
Reset PC = 0x2000_0000.
UART registers (split layout):
| Address | Access | Meaning |
|---|---|---|
0x1000_0000 |
W | TX data — byte to send |
0x1000_0004 |
R | RX data — pops one byte from RX FIFO |
0x1000_0008 |
R | status — bit0 = tx_busy, bit1 = rx_valid |
Building
Requires:
- Vivado 2025.2 or later
- RISC-V GCC toolchain — multilib
riscv64-unknown-elf-gcc. March string evolves with the implementation:rv32im(Phase 8) →rv32im_zicsr_zifencei(Phase 9) →rv32ima_zicsr_zifencei(Phase 12). riscv-tests(for compliance verification from Phase 8.5)- Serial terminal (minicom/picocom/PuTTY) at 115200 8N1
Open FPGA-Core.xpr in Vivado. Synthesis and implementation target the xc7a100tcsg324-1.
Roadmap
See ROADMAP.md for the full phased build plan.
Current Phase
Phase 0 — Architecture contract (package definitions + block diagram)