50 lines
1.6 KiB
Markdown
50 lines
1.6 KiB
Markdown
# Phase 15 - A Extension
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## Context
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The RISC-V A extension adds atomic memory operations. Mainline Linux expects atomics for
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locking, reference counts, futexes, and synchronization.
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## Goals
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- Implement LR/SC.
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- Implement AMO read-modify-write instructions.
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- Run RV32A tests before Linux work.
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## New Concepts
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- Atomic operation: memory operation that appears indivisible to other agents.
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- LR/SC: load-reserved/store-conditional pair.
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- Reservation: remembered address that allows a later store-conditional to succeed.
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- AMO: atomic memory operation combining load, operation, and store.
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## How To Think About It
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In a single-hart, single-master system atomics are conceptually simple. The value is in
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building the right architectural behavior now so the Linux path is realistic later.
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## Learning Tasks
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- Study success and failure cases for `sc.w`.
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- Decide when the reservation is cleared.
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- List AMO operations and their signed/unsigned comparison behavior.
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## Pitfalls
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- Returning the wrong success code from `sc.w`.
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- Forgetting AMOs return the original memory value.
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- Assuming single-hart shortcuts will remain valid if DMA or another master is added.
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## Tooling And Testing
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- Run `rv32ua` tests from riscv-tests or architectural tests.
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- Use memory traces to verify read-modify-write ordering.
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- Test reservation clearing on stores to the reserved address.
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## References
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- RISC-V unprivileged ISA, A extension: https://riscv.org/technical/specifications/
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- riscv-tests: https://github.com/riscv-software-src/riscv-tests
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- Linux atomic operations documentation: https://docs.kernel.org/core-api/wrappers/atomic_t.html
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