imple
b008b37d49
Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
50 lines
1.5 KiB
Markdown
50 lines
1.5 KiB
Markdown
# Phase 5.2 - Jump Instructions
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## Context
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Jumps provide unconditional control transfer and function-call mechanics. `jal` is
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PC-relative; `jalr` jumps through a register plus immediate.
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## Goals
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- Implement `jal` and `jalr`.
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- Store PC + 4 into the destination register.
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- Verify call and return sequences.
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## New Concepts
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- Return address: address of the instruction after the call.
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- Indirect jump: target comes from a register rather than only the instruction.
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- J-type immediate: immediate format used by `jal`.
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- Calling convention: software agreement for argument, return, and saved registers.
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## How To Think About It
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`jal` and `jalr` are both "write link, then redirect PC." The redirect source differs;
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the writeback behavior is shared.
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## Learning Tasks
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- Hand-trace a call and return using `ra` (`x1`).
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- Verify `jalr` target bit 0 clearing.
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- Learn which registers the RISC-V ABI uses for calls.
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## Pitfalls
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- Writing the jump target instead of PC + 4 into `rd`.
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- Mishandling `rd = x0`, which should discard the link.
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- Forgetting `jalr` is commonly used for returns and function pointers.
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## Tooling And Testing
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- Test `jal`, `jalr`, and `jalr x0, ra, 0` return style.
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- Use objdump to confirm labels assemble to expected offsets.
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- Inspect register writeback and PC change in the same trace.
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## References
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- RISC-V unprivileged ISA, jumps: https://riscv.org/technical/specifications/
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- RISC-V ELF psABI: https://github.com/riscv-non-isa/riscv-elf-psabi-doc
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- RISC-V assembly manual: https://github.com/riscv-non-isa/riscv-asm-manual
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