imple
b008b37d49
Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
50 lines
1.6 KiB
Markdown
50 lines
1.6 KiB
Markdown
# Phase 4 - First CPU
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## Context
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This phase connects fetch, decode, arithmetic, register-file, and writeback into a minimal
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non-pipelined CPU. It executes straight-line arithmetic programs from instruction BRAM.
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## Goals
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- Build the first integrated datapath.
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- Learn how BRAM latency shapes control flow.
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- Verify architectural state changes instruction by instruction.
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## New Concepts
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- BRAM: block RAM, dedicated on-chip FPGA memory with synchronous access.
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- PC: program counter, the address of the current or next instruction.
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- Writeback: stage where a result is committed to the register file.
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- CPI: cycles per instruction.
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## How To Think About It
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This is not a performance exercise. It is an integration exercise. The goal is to make
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one instruction at a time retire correctly while respecting real memory latency.
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## Learning Tasks
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- Draw the fetch/execute FSM.
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- Decide exactly when PC advances.
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- Trace a short program and record expected register state after each instruction.
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## Pitfalls
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- Treating BRAM like a combinational array.
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- Updating PC while a multi-cycle M operation is still in progress.
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- Writing back results for instructions that should not write a register.
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## Tooling And Testing
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- Start with very small programs and known final register values.
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- Use simulation waveforms before ILA.
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- Add a visible "halt" or terminal condition for test programs.
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## References
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- AMD/Xilinx block memory documentation: https://docs.xilinx.com/
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- RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
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- Digital design FSM overview: https://www.chipverify.com/verilog/verilog-fsm
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