FPGA-Core/Tutorial/phase-04-first-cpu/phase-04-01-fetch-datapath-integration.md

Phase 4.1 - Fetch + Datapath Integration

Context

This subphase builds the first CPU loop: fetch an instruction, decode it, execute it, write back a result, and advance PC.

Goals

• Integrate instruction BRAM at 0x2000_0000.
• Execute straight-line arithmetic and M-extension operations.
• Learn stall control around BRAM and the M unit.

New Concepts

• Reset PC: address where execution begins after reset.
• FSM state: named control state such as fetch, execute, wait, writeback.
• Instruction retirement: point where an instruction's architectural effects are complete.
• Stall: holding PC/state while waiting for a dependency.

How To Think About It

The CPU is a protocol participant with its memories and M unit. Correct sequencing matters more than minimizing cycles.

Learning Tasks

• Write a cycle-by-cycle timeline for a simple addi instruction.
• Write a cycle-by-cycle timeline for a multiply/divide instruction.
• Confirm the pre-Phase 12 illegal-instruction behavior: halt the core and expose the offending PC and instruction word to the testbench.

Pitfalls

• Double-executing an instruction because PC or state advances at the wrong time.
• Starting the M unit repeatedly while waiting for it to finish.
• Losing the destination register number while a multi-cycle op is in flight.

Tooling And Testing

• Use a testbench that stops after a fixed halt condition or maximum cycle count.
• Compare final register state and intermediate writeback events.
• Inspect PC, instruction, state, register write enable, and writeback data in waveforms.

References

• RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
• Vivado simulation documentation: https://docs.xilinx.com/
• Project F memory initialization: https://projectf.io/posts/initialize-memory-in-verilog/