imple
b008b37d49
Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
49 lines
1.6 KiB
Markdown
49 lines
1.6 KiB
Markdown
# Phase 2.2 - Optional VIO Validation
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## Context
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The register file is simple enough that simulation is usually sufficient, but VIO can
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teach practical debug techniques on real FPGA state.
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## Goals
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- Practice observing and driving register-file signals in hardware.
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- Confirm reset/write/read expectations after synthesis.
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- Learn when hardware debug is worth the overhead.
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## New Concepts
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- Probe: signal connected to debug IP for observation.
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- Debug visibility: whether a net survives optimization and can be inspected.
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- Hardware Manager: Vivado tool for programming and interacting with the FPGA.
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## How To Think About It
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Use VIO here only as a learning exercise. Do not make it a habit to replace systematic
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simulation with manual poking.
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## Learning Tasks
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- Select a minimal set of probes: addresses, write data, write enable, read outputs.
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- Compare one same-cycle read/write case with the simulator.
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- Observe how a clocked write appears relative to your VIO actions.
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## Pitfalls
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- Over-instrumenting and making the debug design harder than the actual module.
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- Forgetting that manual tests rarely cover corner cases.
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- Treating VIO as evidence of complete correctness.
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## Tooling And Testing
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- Keep the VIO wrapper separate from the synthesizable register-file module.
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- Remove or isolate debug IP before building later phases.
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- Check resource utilization with and without debug IP.
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## References
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- Vivado debug documentation: https://docs.xilinx.com/
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- Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
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- LowRISC style guide: https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md
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