51 lines
1.7 KiB
Markdown
51 lines
1.7 KiB
Markdown
# Phase 16 - Pipeline
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## Context
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Pipelining overlaps multiple instructions to improve throughput. This is optional for
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the Linux goal but highly educational for computer architecture.
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## Goals
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- Insert registers between conceptual stages.
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- Handle data and control hazards.
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- Re-run regression tests after changing timing structure.
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## New Concepts
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- Pipeline stage: portion of instruction work separated by registers.
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- Hazard: situation where overlapping instructions would produce wrong behavior.
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- Forwarding: using a result before it reaches the register file.
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- Flush: discarding wrong-path instructions.
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- Stall: holding one or more stages until a hazard clears.
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## How To Think About It
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A pipeline is not just adding registers. It changes when values are available and when
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instructions retire. Correctness depends on explicit hazard handling.
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## Learning Tasks
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- Draw instruction timelines for dependent arithmetic operations.
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- Identify where branch decisions occur and what must be flushed.
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- Decide how multi-cycle M and memory operations interact with the pipeline.
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## Pitfalls
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- Adding pipeline registers before defining valid/kill/stall behavior.
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- Forgetting load-use hazards.
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- Letting exceptions retire out of order.
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## Tooling And Testing
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- Keep a non-pipelined core as a conceptual reference.
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- Run compliance tests before and after each pipeline milestone.
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- Add trace logging of retired instructions if possible.
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## References
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- Computer Organization and Design RISC-V edition: https://shop.elsevier.com/books/computer-organization-and-design-risc-v-edition/patterson/978-0-12-820331-6
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- Hazard overview: https://en.wikipedia.org/wiki/Hazard_(computer_architecture)
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- RISC-V formal interface concepts: https://github.com/SymbioticEDA/riscv-formal
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