53 lines
1.8 KiB
Markdown
53 lines
1.8 KiB
Markdown
# Phase 12 - CSRs + M-Mode Trap Handling
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## Context
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This phase adds architectural control registers and the mechanism for exceptions and
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interrupts. The CPU stops merely halting on faults and starts transferring control to
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software handlers.
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## Goals
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- Implement key machine-mode CSRs.
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- Implement CSR instructions and `mret`.
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- Add trap entry for illegal instructions, breakpoints, ecalls, and access faults.
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## New Concepts
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- CSR: control and status register, special architectural register accessed by CSR instructions.
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- Trap: synchronous exception or asynchronous interrupt that redirects execution.
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- `mepc`: CSR holding PC to return to after a trap.
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- `mcause`: CSR describing why the trap occurred.
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- `mtvec`: CSR holding trap handler address.
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- `mret`: instruction returning from machine-mode trap.
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## How To Think About It
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Traps are controlled context switches within the CPU. Hardware records enough state for
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software to inspect the cause, handle it, and resume or terminate.
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## Learning Tasks
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- Draw the exact state updates on trap entry.
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- Write a table of each exception source and its `mcause`, then compare it with
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the trap-cause decisions in the roadmap.
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- Understand which PC is saved for each exception type.
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## Pitfalls
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- Saving the wrong PC in `mepc`.
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- Updating architectural state for a faulting instruction that should not retire.
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- Treating all exceptions as illegal instructions.
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## Tooling And Testing
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- Create tiny programs that intentionally trigger one exception at a time.
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- Inspect CSR values after trap entry in simulation.
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- Test `mret` returning to a known instruction address.
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## References
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- RISC-V privileged architecture spec: https://riscv.org/technical/specifications/
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- RISC-V CSR instruction semantics: https://riscv.org/technical/specifications/
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- RISC-V educational trap handling notes: https://osblog.stephenmarz.com/
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