imple
b008b37d49
Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
50 lines
1.6 KiB
Markdown
50 lines
1.6 KiB
Markdown
# Phase 8.3 - Fill Remaining RV32I Gaps
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## Context
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Compiler output will expose missing instructions and edge cases. This subphase closes
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the base ISA gaps before moving into traps and privilege.
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## Goals
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- Implement remaining RV32I instructions required by compiler output.
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- Decode `fence` as safe in a cacheless design.
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- Make unsupported system instructions halt visibly.
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## New Concepts
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- `fence`: memory-ordering instruction.
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- `fence.i`: instruction-stream synchronization instruction.
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- `ecall`: environment call, later a trap.
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- `ebreak`: breakpoint instruction, later a trap.
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## How To Think About It
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Incomplete ISA behavior should be loud. A clean halt with PC and instruction word is far
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better than silent execution through an unsupported instruction.
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## Learning Tasks
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- Make a list of every RV32I instruction and current support status.
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- Disassemble increasingly complex C programs and mark new instructions.
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- Understand why `fence` can be harmless without caches while `fence.i` still needs decode policy.
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## Pitfalls
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- Treating `ecall` or `ebreak` as NOPs.
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- Missing uncommon instructions emitted by switch statements or stack setup.
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- Debugging firmware before checking the disassembly.
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## Tooling And Testing
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- Add illegal-instruction tests.
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- Keep a cycle limit in simulations to catch hangs.
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- Use compiler output as a test source, not a proof of correctness.
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## References
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- RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
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- GCC RISC-V options: https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html
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- RISC-V assembly manual: https://github.com/riscv-non-isa/riscv-asm-manual
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