49 lines
1.6 KiB
Markdown
49 lines
1.6 KiB
Markdown
# Phase 7 - Memory-Mapped UART
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## Context
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This phase connects software-visible memory addresses to a peripheral. UART becomes the
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first external communication path driven by CPU instructions.
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## Goals
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- Build standalone TX and RX UART blocks.
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- Map UART registers into the D-bus address space.
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- Print a message from software running on the CPU.
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## New Concepts
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- MMIO: memory-mapped I/O; device registers accessed with normal loads/stores.
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- Address decoder: logic routing addresses to selected slaves.
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- Status register: read-only register exposing peripheral state.
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- FIFO: queue buffering bytes between producer and consumer.
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## How To Think About It
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The CPU should not know about UART internals. It issues stores and loads; the bus decoder
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and peripheral register file translate those into device behavior.
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## Learning Tasks
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- Draw the UART register map.
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- Decide what happens if software writes while TX is busy.
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- Decide when RX data is consumed and status changes.
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## Pitfalls
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- Making register side effects ambiguous.
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- Forgetting software must poll status before writes.
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- Combining peripheral timing with CPU timing too tightly.
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## Tooling And Testing
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- Verify UART standalone before MMIO integration.
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- Use a terminal for end-to-end tests and ILA for bus/peripheral mismatches.
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- Keep register behavior documented for firmware authors.
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## References
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- Digilent Arty A7 USB-UART notes: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
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- RISC-V platform-level interrupt spec for later context: https://github.com/riscv/riscv-plic-spec
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- Memory-mapped I/O overview: https://en.wikipedia.org/wiki/Memory-mapped_I/O
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