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imple b008b37d49 Add phase-by-phase tutorial notes

Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up.
Each phase and subphase gets a short learning note with consistent sections for
context, goals, new concepts, mental model, learning tasks, pitfalls, tooling,
testing, and references.

The tutorial material is intentionally explanatory rather than implementation
code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V,
firmware, and Linux bring-up context to approach each roadmap phase without
turning the notes into copy-paste RTL.

2026-04-28 12:11:23 +02:00

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Phase 6.2 - Byte And Halfword Access

Context

Sub-word memory operations make C programs practical. char, short, strings, and packed data all depend on byte and halfword accesses.

Goals

Implement lb, lbu, lh, lhu, sb, and sh.
Handle byte lanes and sign/zero extension.
Trap misaligned accesses locally in the LSU.

New Concepts

Sign extension: preserving negative value when widening a smaller signed type.
Zero extension: widening an unsigned value by filling high bits with zero.
Byte enable: control bit selecting which byte lane is written.
Misaligned access: address not divisible by the access size.

How To Think About It

Stores are about choosing byte lanes. Loads are about extracting the correct lane and extending it correctly. Misalignment is known before the bus request starts.

Learning Tasks

Map address low bits to byte lanes.
Work through examples loading 0x80 as signed and unsigned byte.
Decide how halfword alignment is detected.

Pitfalls

Applying sign extension before selecting the correct byte/halfword.
Letting a misaligned request reach memory.
Confusing endianness with bit numbering in diagrams.

Tooling And Testing

Test every byte offset for sb and lb/lbu.
Test halfword offsets 0 and 2 as legal and 1 and 3 as misaligned.
Use memory initialization patterns that make byte order obvious.

References

RISC-V unprivileged ISA load/store chapter: https://riscv.org/technical/specifications/
Endianness overview: https://en.wikipedia.org/wiki/Endianness
Project F memory articles: https://projectf.io/posts/

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