50 lines
1.7 KiB
Markdown
50 lines
1.7 KiB
Markdown
# Phase 0.2 - Block Diagram
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## Context
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The block diagram is the visual source of truth for the datapath. It should show what
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talks to what, what is registered, and what can stall.
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## Goals
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- Draw fetch, decode, register file, ALU, M unit, memory/LSU, and writeback.
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- Label stage-boundary structs from the package.
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- Mark clocked state, combinational paths, handshakes, and reset behavior.
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## New Concepts
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- Datapath: the route operands and results take through the CPU.
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- Control path: signals that choose operations, mux inputs, stalls, and traps.
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- Mux: hardware selector that chooses one of several inputs.
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- Stall: deliberately holding state while waiting for a multi-cycle event.
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## How To Think About It
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Draw movement of information, not just boxes. A useful hardware diagram answers: where is
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state stored, what changes each clock, what can wait, and what happens on an exception?
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## Learning Tasks
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- Use arrows for data flow and separate arrows for control when helpful.
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- Mark every register or memory with a clock edge symbol.
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- Identify the longest combinational path you expect in early phases.
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## Pitfalls
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- Drawing BRAM like a zero-latency array.
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- Forgetting that multi-cycle units need explicit state and stall control.
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- Hiding reset and trap paths because they are visually inconvenient.
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## Tooling And Testing
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- Keep the diagram in `Docs/` and update it when interfaces change.
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- Compare waveform signal names against the diagram after each integration phase.
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- Use the diagram as a checklist when adding ILA probes.
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## References
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- nand2tetris CPU/data-path intuition: https://www.nand2tetris.org/
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- RISC-V reader for datapath examples: http://www.riscvbook.com/
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- Vivado ILA overview: https://docs.xilinx.com/
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