44 lines
1.5 KiB
Tcl
44 lines
1.5 KiB
Tcl
# create_project.tcl — generate FPGA/vivado/FPGA-Core.xpr
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#
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# Usage (from the repo root):
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# vivado -mode batch -source FPGA/vivado/create_project.tcl
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#
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# Or from inside FPGA/vivado/:
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# vivado -mode batch -source create_project.tcl
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#
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# Then open the resulting .xpr in the Vivado GUI. To regenerate from scratch,
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# delete FPGA-Core.xpr and its sibling *.cache / *.runs / *.hw / *.sim /
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# *.ip_user_files / *.gen directories, then re-run.
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set script_dir [file normalize [file dirname [info script]]]
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set fpga_dir [file normalize "$script_dir/.."]
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set proj_name "FPGA-Core"
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set part "xc7a100tcsg324-1"
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if {[file exists "$script_dir/$proj_name.xpr"]} {
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puts "Project already exists: $script_dir/$proj_name.xpr"
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puts "Delete it (and its sibling *.cache, *.runs, ... dirs) first."
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return
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}
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create_project $proj_name $script_dir -part $part
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set_property target_language Verilog [current_project]
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set_property simulator_language Mixed [current_project]
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# RTL and testbenches are added as references (not copied) so the source of
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# truth stays in git, not inside the .xpr. Passing a directory makes Vivado
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# recursively pick up all HDL files under it.
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add_files "$fpga_dir/rtl"
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add_files -fileset sim_1 "$fpga_dir/tb"
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set xdc_files [glob -nocomplain "$fpga_dir/constraints/*.xdc"]
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if {[llength $xdc_files] > 0} {
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add_files -fileset constrs_1 $xdc_files
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}
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update_compile_order -fileset sources_1
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update_compile_order -fileset sim_1
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puts "Created $script_dir/$proj_name.xpr"
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