Add phase-by-phase tutorial notes

Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up.
Each phase and subphase gets a short learning note with consistent sections for
context, goals, new concepts, mental model, learning tasks, pitfalls, tooling,
testing, and references.

The tutorial material is intentionally explanatory rather than implementation
code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V,
firmware, and Linux bring-up context to approach each roadmap phase without
turning the notes into copy-paste RTL.

Tutorial/phase-06-load-store/phase-06-01-word-load-store.md

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+# Phase 6.1 - Word Load/Store
+
+## Context
+
+Word loads and stores are the first data-memory operations. They are simpler because
+addresses must be 4-byte aligned and all byte lanes are active.
+
+## Goals
+
+- Add data BRAM.
+- Issue D-bus requests for `lw` and `sw`.
+- Learn request/response sequencing for loads.
+
+## New Concepts
+
+- Word: 32-bit value in RV32.
+- Aligned access: address is a multiple of access size.
+- Response latency: time from request acceptance to returned data.
+- Bus decoder: logic that routes an address to the right memory/peripheral.
+
+## How To Think About It
+
+A store is mostly "send address and data." A load is "send address, wait for response,
+then write back." That waiting must be explicit in the control FSM.
+
+## Learning Tasks
+
+- Draw a timeline for `sw` and `lw`.
+- Mark when `req_valid`, `req_ready`, `rsp_valid`, and `rsp_ready` are meaningful.
+- Decide what state is retained while waiting for load data.
+
+## Pitfalls
+
+- Writing back load data before BRAM response is valid.
+- Advancing PC before a load has completed.
+- Forgetting to tie unused `amo` and sub-word strobes consistently.
+
+## Tooling And Testing
+
+- Start with store-then-load of one word.
+- Add tests for first and last valid data BRAM addresses.
+- Use waveform checks for request acceptance and response timing.
+
+## References
+
+- RISC-V unprivileged ISA loads/stores: https://riscv.org/technical/specifications/
+- Vivado BRAM documentation: https://docs.xilinx.com/
+- AXI valid/ready concepts: https://developer.arm.com/documentation/ihi0022/latest
+

Tutorial/phase-06-load-store/phase-06-02-byte-halfword-access.md

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+# Phase 6.2 - Byte And Halfword Access
+
+## Context
+
+Sub-word memory operations make C programs practical. `char`, `short`, strings, and packed
+data all depend on byte and halfword accesses.
+
+## Goals
+
+- Implement `lb`, `lbu`, `lh`, `lhu`, `sb`, and `sh`.
+- Handle byte lanes and sign/zero extension.
+- Trap misaligned accesses locally in the LSU.
+
+## New Concepts
+
+- Sign extension: preserving negative value when widening a smaller signed type.
+- Zero extension: widening an unsigned value by filling high bits with zero.
+- Byte enable: control bit selecting which byte lane is written.
+- Misaligned access: address not divisible by the access size.
+
+## How To Think About It
+
+Stores are about choosing byte lanes. Loads are about extracting the correct lane and
+extending it correctly. Misalignment is known before the bus request starts.
+
+## Learning Tasks
+
+- Map address low bits to byte lanes.
+- Work through examples loading `0x80` as signed and unsigned byte.
+- Decide how halfword alignment is detected.
+
+## Pitfalls
+
+- Applying sign extension before selecting the correct byte/halfword.
+- Letting a misaligned request reach memory.
+- Confusing endianness with bit numbering in diagrams.
+
+## Tooling And Testing
+
+- Test every byte offset for `sb` and `lb/lbu`.
+- Test halfword offsets 0 and 2 as legal and 1 and 3 as misaligned.
+- Use memory initialization patterns that make byte order obvious.
+
+## References
+
+- RISC-V unprivileged ISA load/store chapter: https://riscv.org/technical/specifications/
+- Endianness overview: https://en.wikipedia.org/wiki/Endianness
+- Project F memory articles: https://projectf.io/posts/
+

Tutorial/phase-06-load-store/phase-06-03-ila-memory-bus.md

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+# Phase 6.3 - ILA On The Memory Bus
+
+## Context
+
+Memory bugs often need cycle-level visibility. ILA on the D-bus lets you see requests,
+responses, byte strobes, and stalls in real hardware.
+
+## Goals
+
+- Learn practical bus-level debug with ILA.
+- Capture load/store transactions.
+- Compare hardware memory behavior with simulation.
+
+## New Concepts
+
+- Transaction: one logical memory operation, possibly spanning multiple cycles.
+- Probe grouping: collecting related signals for readable waveforms.
+- Trigger condition: event that starts capture.
+
+## How To Think About It
+
+Probe at protocol boundaries. If the LSU and memory disagree, the bus waveform tells you
+which side violated the contract.
+
+## Learning Tasks
+
+- Choose probes for D-bus request payload, request handshake, response payload, response handshake.
+- Create one program with predictable stores and loads.
+- Trigger on a target address or final store.
+
+## Pitfalls
+
+- Capturing only data and not the valid/ready signals.
+- Forgetting byte strobes when debugging sub-word stores.
+- Using ILA before simulation has narrowed the failure.
+
+## Tooling And Testing
+
+- Use short programs so captures fit in ILA memory.
+- Keep memory addresses distinctive and easy to recognize.
+- Re-run timing after adding ILA probes.
+
+## References
+
+- Vivado ILA documentation: https://docs.xilinx.com/
+- Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
+- Wishbone spec for bus-debug vocabulary: https://cdn.opencores.org/downloads/wbspec_b4.pdf
+

Tutorial/phase-06-load-store/phase-06.md

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+# Phase 6 - Load/Store
+
+## Context
+
+Load/store connects the CPU to data memory and later to memory-mapped devices. RISC-V is
+a load/store architecture: arithmetic works on registers, memory access is explicit.
+
+## Goals
+
+- Add data BRAM at `0x8000_0000`.
+- Define and use the D-bus contract.
+- Support word, byte, and halfword memory operations.
+
+## New Concepts
+
+- LSU: load/store unit, responsible for address generation and data formatting.
+- D-bus: data-side memory request/response channel.
+- Byte lane: one of the four bytes in a 32-bit word.
+- Write strobe: byte-enable mask for sub-word stores.
+
+## How To Think About It
+
+Memory operations are protocol transactions. Address alignment, byte selection, sign
+extension, response timing, and error classification all matter.
+
+## Learning Tasks
+
+- Draw how a byte store updates one lane of a 32-bit word.
+- Decide how the LSU detects misalignment before bus issue.
+- Trace a load from execute through response and writeback.
+
+## Pitfalls
+
+- Returning unshifted data for byte/halfword loads.
+- Treating misalignment as a bus error instead of an architectural exception.
+- Forgetting stores do not write back to the register file.
+
+## Tooling And Testing
+
+- Test all byte offsets within a word.
+- Use memory dumps or waveform inspection for store byte lanes.
+- Add maximum cycle timeouts to catch hung bus handshakes.
+
+## References
+
+- RISC-V load/store semantics: https://riscv.org/technical/specifications/
+- AMD/Xilinx block RAM documentation: https://docs.xilinx.com/
+- Wishbone bus spec for handshake comparison: https://cdn.opencores.org/downloads/wbspec_b4.pdf
+