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Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
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Phase 6.3 - ILA On The Memory Bus
Context
Memory bugs often need cycle-level visibility. ILA on the D-bus lets you see requests, responses, byte strobes, and stalls in real hardware.
Goals
- Learn practical bus-level debug with ILA.
- Capture load/store transactions.
- Compare hardware memory behavior with simulation.
New Concepts
- Transaction: one logical memory operation, possibly spanning multiple cycles.
- Probe grouping: collecting related signals for readable waveforms.
- Trigger condition: event that starts capture.
How To Think About It
Probe at protocol boundaries. If the LSU and memory disagree, the bus waveform tells you which side violated the contract.
Learning Tasks
- Choose probes for D-bus request payload, request handshake, response payload, response handshake.
- Create one program with predictable stores and loads.
- Trigger on a target address or final store.
Pitfalls
- Capturing only data and not the valid/ready signals.
- Forgetting byte strobes when debugging sub-word stores.
- Using ILA before simulation has narrowed the failure.
Tooling And Testing
- Use short programs so captures fit in ILA memory.
- Keep memory addresses distinctive and easy to recognize.
- Re-run timing after adding ILA probes.
References
- Vivado ILA documentation: https://docs.xilinx.com/
- Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
- Wishbone spec for bus-debug vocabulary: https://cdn.opencores.org/downloads/wbspec_b4.pdf