Tighten memory bus and trap ownership contracts
Convert the memory-bus guidance from a loose list of request/response fields into packed mem_req_t and mem_rsp_t payload structs carried by separate valid/ready handshakes. Spell out that the same channel shape is instantiated independently for the instruction bus and data bus so the design remains Harvard at the bus level while still sharing a single contract. Clarify fault ownership before RTL exists: slaves only raise rsp.err for access faults they can own, the LSU detects misaligned loads/stores before issuing a D-bus request, the decoder owns illegal instructions and ebreak/ecall decode events, and the future MMU owns page faults before translated requests reach the bus. Update the roadmap to use the structured bus field names, correct the misalignment tests and GCC illegal-instruction explanation, and prefer modern RISC-V device-tree ISA properties with an optional legacy riscv,isa string for older kernels.
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## Project Overview
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This is a custom RISC-V RV32IM CPU core written in SystemVerilog, targeting the
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Digilent Arty A7 100T (xc7a100tcsg324-1) with Vivado 2025.2 or later.
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This is a custom RISC-V CPU core written in SystemVerilog, targeting the
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Digilent Arty A7 100T (xc7a100tcsg324-1) with Vivado 2025.2 or later. It
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starts as RV32IM and grows toward **RV32IMA + Zicsr + Zifencei + M/S/U
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privilege + Sv32** for a Linux-capable SoC.
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The goal is incremental development from a single-cycle core to a Linux-capable SoC.
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See ROADMAP.md for the full phased plan.
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## Conventions
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@@ -104,38 +105,110 @@ or write a custom Linux serial driver + device-tree binding.
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## Memory Bus Contract
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Single channel, valid/ready handshake, defined once in `rv32_pkg.sv` and
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reused by every master/slave (CPU, instruction BRAM, data BRAM, MMIO,
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DRAM later). Master drives a request, slave drives a response.
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Single channel shape, valid/ready handshake, defined once in `rv32_pkg.sv`.
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Each channel has two parts: a **payload struct** (single-direction) and a
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loose **valid/ready handshake pair** (one signal in each direction). The
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payload structs are packed and directional; valid/ready stays outside the
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struct to avoid mixing directions.
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```
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Request (master → slave):
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req_valid : logic — request is valid this cycle
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req_ready : logic — slave accepts (driven by slave)
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req_addr : logic [31:0] — byte address
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req_we : logic — 1 = write, 0 = read
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req_size : logic [1:0] — 00=byte, 01=halfword, 10=word
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req_wdata : logic [31:0] — write data (lane-aligned per wstrb)
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req_wstrb : logic [3:0] — byte enables (writes only)
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The same channel shape is **instanced twice** — once for the I-bus
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(fetch ↔ instruction memory) and once for the D-bus (LSU ↔ data memory and
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MMIO). Harvard at the bus level, not just at the BRAM level.
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Response (slave → master):
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rsp_valid : logic — response is valid this cycle
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rsp_ready : logic — master accepts (driven by master)
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rsp_rdata : logic [31:0] — read data (reads only)
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rsp_err : logic — fault: unmapped, misaligned, access violation
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```systemverilog
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// Payload — master → slave
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typedef struct packed {
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logic [31:0] addr;
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logic we; // 1 = write, 0 = read (always 0 on I-bus)
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logic [1:0] size; // 00=byte, 01=halfword, 10=word
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logic [31:0] wdata; // lane-aligned per wstrb
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logic [3:0] wstrb; // byte enables (writes only)
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logic [3:0] amo; // AMO op encoding (D-bus only, Phase 12+)
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} mem_req_t;
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// Payload — slave → master
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typedef struct packed {
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logic [31:0] rdata; // valid on reads only
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logic err; // slave-reported access fault
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} mem_rsp_t;
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// Per-channel signals (instance once for I-bus, once for D-bus):
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// logic <ch>_req_valid; // master → slave
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// logic <ch>_req_ready; // slave → master
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// mem_req_t <ch>_req; // master → slave
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//
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// logic <ch>_rsp_valid; // slave → master
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// logic <ch>_rsp_ready; // master → slave
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// mem_rsp_t <ch>_rsp; // slave → master
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```
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Notes:
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- `req_valid`/`req_ready` and `rsp_valid`/`rsp_ready` are independent
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handshakes; a slave may take multiple cycles between accepting a request
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and producing a response (BRAM = 1 cycle, DRAM = many).
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- `req_wstrb` is mandatory from Phase 6.2 onward (sub-word stores). For
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If you later prefer a SystemVerilog `interface`, use master/slave modports
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to enforce direction. Until then, loose signals + payload structs are the
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simplest path that survives every Vivado quirk.
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Handshake notes:
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- Standard valid/ready: a beat transfers when both `valid` and `ready` are
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high in the same cycle. Request and response handshakes are independent;
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a slave may take multiple cycles between accepting a request and
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producing a response (BRAM = 1 cycle, DRAM = many).
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- `wstrb` is mandatory from Phase 6.2 onward (sub-word stores). For
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Phase 6.1 (word-only), tie strobes to `4'b1111` on stores.
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- `rsp_err` lets the bus signal misalignment, unmapped MMIO, and (later)
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page faults uniformly. The CPU's trap logic (Phase 9) consumes it as
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load/store access-fault exceptions.
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- Atomics (Phase 12) extend this with an `req_amo` opcode field rather than
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a new bus.
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- `amo` is unused (drive `4'h0`) until Phase 12; on the I-bus it is always
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unused.
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- `err` is **only** raised by a slave to report access faults it owns:
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unmapped address, peripheral-access violation, eventually DRAM ECC fault.
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It does NOT carry misalignment (the LSU detects that locally and never
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issues), illegal instructions (decode event, not bus), or page faults
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(MMU generates them before the bus). Keeping `err` to one bit is fine
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because the master that issued the transaction has all the context
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needed to classify it.
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### I-bus / D-bus instance plan
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Both buses use the same `mem_req_t` / `mem_rsp_t` struct, instanced
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separately. Per-phase progression:
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| Phase | I-bus | D-bus |
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|-------|--------------------------------|---------------------------------------------|
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| 4 | CPU fetch ↔ instruction BRAM | (none yet) |
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| 6 | unchanged | LSU ↔ data BRAM (single slave) |
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| 7 | unchanged | LSU ↔ decoder → {data BRAM, UART MMIO} |
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| 9-12 | unchanged | + timer (Phase 10), PLIC (Phase 11) |
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| 14 | I-bus → arbiter → DRAM | D-bus → arbiter → DRAM (or MIG dual-port) |
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Both buses can fault independently; classification happens in the masters
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(see below).
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### Trap cause classification (who owns which mcause)
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`rsp.err` is one bit on the wire. The **master** that issued the
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transaction adds context to produce the precise architectural cause:
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| Source | mcause | Detected by |
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|-------------------------------------|--------|-----------------------------------|
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| Instruction address misaligned | 0 | fetch unit (PC[1:0] != 0) |
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| Instruction access fault | 1 | fetch unit (I-bus `rsp.err`) |
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| Illegal instruction | 2 | decoder (`illegal_instr`) |
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| Breakpoint (`ebreak`) | 3 | decoder |
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| Load address misaligned | 4 | LSU (size + addr LSBs, pre-issue) |
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| Load access fault | 5 | LSU (D-bus `rsp.err` on read) |
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| Store/AMO address misaligned | 6 | LSU (size + addr LSBs, pre-issue) |
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| Store/AMO access fault | 7 | LSU (D-bus `rsp.err` on write) |
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| Ecall from M-mode | 11 | decoder |
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| Instruction page fault | 12 | I-side MMU (Phase 15) |
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| Load page fault | 13 | D-side MMU (Phase 15) |
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| Store/AMO page fault | 15 | D-side MMU (Phase 15) |
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Two consequences:
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- The LSU detects misalignment **before** issuing a bus request — never
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send a request you already know will trap.
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- Page faults (Phase 15) are raised by the MMU during translation,
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before the (translated) request hits the bus.
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### Atomics (Phase 12)
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LR/SC and AMO use the `amo` field of `mem_req_t` (D-bus only) rather than
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a separate bus. Single-hart reservation tracking lives in the LSU.
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## When Helping With This Project
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