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Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
1.7 KiB
1.7 KiB
Phase 14 - SPI Flash Boot + DRAM
Context
BRAM is small and initialized by the FPGA bitstream. A Linux-capable system needs persistent boot storage and much larger RAM, so this phase adds flash boot and DDR3L.
Goals
- Boot from on-board SPI flash.
- Integrate DDR3L through the Xilinx MIG IP.
- Move executable images into DRAM and run from there.
New Concepts
- SPI flash: serial nonvolatile storage on the board.
- DRAM: external dynamic memory requiring a controller and refresh.
- MIG: Xilinx Memory Interface Generator IP for DDR memory controllers.
- Bootloader: small program that prepares memory and jumps to a larger image.
- Arbiter: logic choosing which bus master accesses shared memory.
How To Think About It
This is the first major SoC integration phase. External memory is not a simple array: latency varies, calibration matters, and reset sequencing becomes important.
Learning Tasks
- Understand the Arty A7 memory devices and their address ranges.
- Draw boot flow from reset to flash fetch to DRAM copy to jump.
- Decide how I-bus and D-bus arbitrate for DRAM.
Pitfalls
- Assuming DRAM is ready immediately after FPGA reset.
- Ignoring MIG clocking and reset requirements.
- Mixing boot ROM, flash aperture, and DRAM addresses without a clear map.
Tooling And Testing
- Validate DRAM with a standalone memory test before CPU boot.
- Use ILA around MIG app interface and bus arbiter.
- Keep a tiny BRAM-resident fallback test path while debugging flash/DRAM.
References
- Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
- AMD/Xilinx MIG documentation: https://docs.xilinx.com/
- JEDEC DDR background: https://www.jedec.org/standards-documents/focus/memory-module-design