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imple b008b37d49 Add phase-by-phase tutorial notes

Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up.
Each phase and subphase gets a short learning note with consistent sections for
context, goals, new concepts, mental model, learning tasks, pitfalls, tooling,
testing, and references.

The tutorial material is intentionally explanatory rather than implementation
code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V,
firmware, and Linux bring-up context to approach each roadmap phase without
turning the notes into copy-paste RTL.

2026-04-28 12:11:23 +02:00

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Phase 3.1 - Instruction Decoder

Context

This subphase creates the combinational decoder module that turns raw instruction bits into decode_out_t fields.

Goals

Decode source/destination registers, immediates, ALU operation, memory operation, and branch type.
Identify legal versus illegal instructions.
Verify all instruction formats with known encodings.

New Concepts

Sign extension: copying a sign bit into higher bits to preserve signed value.
Zero extension: filling upper bits with zero.
Control signal: a signal that chooses what hardware action occurs.
Decode table: mapping from instruction fields to operation semantics.

How To Think About It

Decoder bugs often look like random CPU bugs later. Invest heavily here. If an immediate bit is wrong, the ALU and branch logic can be perfect and the program will still fail.

Learning Tasks

Create a checklist for each instruction family and expected decode fields.
For each immediate format, manually reconstruct the value from bit positions.
Decide how fence, fence.i, CSR, ecall, and ebreak are represented before traps exist.

Pitfalls

Copying immediate extraction logic without understanding bit order.
Missing jalr's low-bit clearing rule later in execute/control flow.
Letting default decode outputs accidentally describe a valid NOP.

Tooling And Testing

Generate encodings with the RISC-V assembler, not by hand alone.
Use objdump to verify that your test words are the instructions you think they are.
Add negative tests for illegal encodings.

References

RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
RISC-V opcode repository: https://github.com/riscv/riscv-opcodes
GNU assembler manual: https://sourceware.org/binutils/docs/as/

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