FPGA-Core/FPGA/vivado

FPGA/vivado/

The Vivado project workspace. The committed source of truth is create_project.tcl; the project file (FPGA-Core.xpr) and all of Vivado's generated state (*.runs/, *.cache/, *.hw/, *.sim/, *.ip_user_files/, *.gen/, *.srcs/) are git-ignored — .xpr files embed machine-specific paths and are regenerated locally.

RTL and testbench files are added to the project as references to ../rtl/... / ../tb/... so the actual source of truth stays in version control, not inside the project file.

To generate the project, run from the repo root:

vivado -mode batch -source FPGA/vivado/create_project.tcl

Then open the resulting FPGA/vivado/FPGA-Core.xpr in the Vivado GUI.