imple
b008b37d49
Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up. Each phase and subphase gets a short learning note with consistent sections for context, goals, new concepts, mental model, learning tasks, pitfalls, tooling, testing, and references. The tutorial material is intentionally explanatory rather than implementation code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V, firmware, and Linux bring-up context to approach each roadmap phase without turning the notes into copy-paste RTL.
1.5 KiB
1.5 KiB
Phase 7.4 - Hello World
Context
This is the first user-visible proof that software running on your CPU can communicate with the outside world through MMIO.
Goals
- Run a hand-written assembly program from instruction BRAM.
- Poll UART status and write bytes to TX data.
- Verify output in a terminal.
New Concepts
- Polling: repeatedly reading status until a condition is true.
- Firmware: low-level software running directly on the hardware.
- Memory-mapped register access: using load/store instructions to control a device.
How To Think About It
This milestone tests the full vertical slice: instruction fetch, decode, ALU, branches, loads/stores, bus decode, UART, board pinout, and terminal settings.
Learning Tasks
- Trace each instruction in the polling loop.
- Explain why the program waits for
tx_busyto clear. - Identify every hardware block involved in printing one character.
Pitfalls
- Terminal configured for the wrong baud or line settings.
- Writing bytes without checking busy status.
- Debugging UART first when the actual bug is branch/load/store behavior.
Tooling And Testing
- First verify UART standalone.
- In hardware, probe UART status and D-bus writes if the terminal is silent.
- Keep the program tiny and deterministic.
References
- RISC-V assembly manual: https://github.com/riscv-non-isa/riscv-asm-manual
- Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
- UART overview: https://en.wikipedia.org/wiki/Universal_asynchronous_receiver-transmitter