Files

T

imple b008b37d49 Add phase-by-phase tutorial notes

Add a Tutorial tree that mirrors the roadmap from Phase 0 through Linux bring-up.
Each phase and subphase gets a short learning note with consistent sections for
context, goals, new concepts, mental model, learning tasks, pitfalls, tooling,
testing, and references.

The tutorial material is intentionally explanatory rather than implementation
code. It gives a systems-oriented learner enough FPGA, SystemVerilog, RISC-V,
firmware, and Linux bring-up context to approach each roadmap phase without
turning the notes into copy-paste RTL.

2026-04-28 12:11:23 +02:00

1.6 KiB

Raw Permalink Blame History

Phase 2 - Register File

Context

The register file is the CPU's small, fast architectural storage. RISC-V has 32 integer registers, with x0 permanently reading as zero.

Goals

Build a 32 x 32-bit register file with two reads and one write.
Define same-cycle read/write behavior intentionally.
Learn how small memories map onto FPGA resources.

New Concepts

Read port: ability to read one register address in a cycle.
Write port: ability to update one register address on a clock edge.
Architectural register: register visible to software.
Hardwired zero: x0 ignores writes and always returns zero.

How To Think About It

The register file is part storage and part contract with the ISA. Its behavior must be boring, predictable, and heavily tested because every instruction depends on it.

Learning Tasks

Decide whether same-cycle read-after-write returns old or new data.
Make a register naming table from ABI names to x numbers.
Understand why two read ports are enough for RV32I/RV32M.

Pitfalls

Accidentally allowing writes to x0.
Assuming FPGA block RAM behavior without checking read-port needs.
Leaving same-cycle behavior unspecified until integration exposes it.

Tooling And Testing

Test all boundary addresses: x0, x1, x31.
Test simultaneous reads of two different registers and the same register.
Prefer a waveform check for one read/write collision case.

References

RISC-V register convention: https://riscv.org/technical/specifications/
AMD/Xilinx memory resources: https://docs.xilinx.com/
Project F memory initialization and FPGA memories: https://projectf.io/posts/

1.6 KiB Raw Permalink Blame History