# Phase 6.3 - ILA On The Memory Bus

## Context

Memory bugs often need cycle-level visibility. ILA on the D-bus lets you see requests,
responses, byte strobes, and stalls in real hardware.

## Goals

- Learn practical bus-level debug with ILA.
- Capture load/store transactions.
- Compare hardware memory behavior with simulation.

## New Concepts

- Transaction: one logical memory operation, possibly spanning multiple cycles.
- Probe grouping: collecting related signals for readable waveforms.
- Trigger condition: event that starts capture.

## How To Think About It

Probe at protocol boundaries. If the LSU and memory disagree, the bus waveform tells you
which side violated the contract.

## Learning Tasks

- Choose probes for D-bus request payload, request handshake, response payload, response handshake.
- Create one program with predictable stores and loads.
- Trigger on a target address or final store.

## Pitfalls

- Capturing only data and not the valid/ready signals.
- Forgetting byte strobes when debugging sub-word stores.
- Using ILA before simulation has narrowed the failure.

## Tooling And Testing

- Use short programs so captures fit in ILA memory.
- Keep memory addresses distinctive and easy to recognize.
- Re-run timing after adding ILA probes.

## References

- Vivado ILA documentation: https://docs.xilinx.com/
- Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual
- AXI-Lite valid/ready concepts for bus-debug vocabulary: https://developer.arm.com/documentation/ihi0022/latest