# Phase 1.3 - ALU + M Unit On FPGA With VIO

## Context

After simulation, place the arithmetic blocks on real hardware and interact with them
through Vivado VIO. This teaches the difference between simulated correctness and
synthesized hardware behavior.

## Goals

- Learn how to instantiate debug IP around simple modules.
- Confirm arithmetic blocks synthesize and meet the 50 MHz target.
- Practice observing handshake behavior in hardware.

## New Concepts

- VIO: Vivado Virtual Input/Output IP, controlled over JTAG.
- JTAG: debug/control link used by Vivado Hardware Manager.
- Timing closure: proving signals settle before the next clock edge.
- Synthesis: compiling RTL into FPGA primitives.

## How To Think About It

This is not about exhaustive validation. It is about learning the FPGA tool loop:
synthesize, implement, program, poke signals, observe results, and read timing reports.

## Learning Tasks

- Identify which signals are useful to drive and which are useful to observe.
- Read the timing summary and locate the worst path.
- Compare VIO observations with simulator waveforms.

## Pitfalls

- Letting Vivado optimize away debug signals before VIO/ILA can observe them.
- Confusing VIO interaction latency with the design's actual clock-cycle behavior.
- Ignoring timing warnings because the manual test "seemed to work."

## Tooling And Testing

- Use VIO for low-bandwidth manual checks, not automated compliance.
- Keep a short lab notebook: bitstream, clock, operands, expected, observed.
- Learn where Vivado reports resource use for LUTs, FFs, DSPs, and BRAMs.

## References

- Vivado Design Suite documentation: https://docs.xilinx.com/
- Vivado debug IP overview: https://docs.xilinx.com/
- Digilent Arty A7 reference: https://digilent.com/reference/programmable-logic/arty-a7/reference-manual