# Phase 8.3 - Fill Remaining RV32I Gaps

## Context

Compiler output will expose missing instructions and edge cases. This subphase closes
the base ISA gaps before moving into traps and privilege.

## Goals

- Implement remaining RV32I instructions required by compiler output.
- Decode `fence` as safe in a cacheless design.
- Make unsupported system instructions halt visibly.

## New Concepts

- `fence`: memory-ordering instruction.
- `fence.i`: instruction-stream synchronization instruction.
- `ecall`: environment call, later a trap.
- `ebreak`: breakpoint instruction, later a trap.

## How To Think About It

Incomplete ISA behavior should be loud. A clean halt with PC and instruction word is far
better than silent execution through an unsupported instruction.

## Learning Tasks

- Make a list of every RV32I instruction and current support status.
- Disassemble increasingly complex C programs and mark new instructions.
- Understand why `fence` can be harmless without caches while `fence.i` still needs decode policy.

## Pitfalls

- Treating `ecall` or `ebreak` as NOPs.
- Missing uncommon instructions emitted by switch statements or stack setup.
- Debugging firmware before checking the disassembly.

## Tooling And Testing

- Add illegal-instruction tests.
- Keep a cycle limit in simulations to catch hangs.
- Use compiler output as a test source, not a proof of correctness.

## References

- RISC-V unprivileged ISA: https://riscv.org/technical/specifications/
- GCC RISC-V options: https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html
- RISC-V assembly manual: https://github.com/riscv-non-isa/riscv-asm-manual